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d a t a sh eet product speci?cation supersedes data of september 1993 file under integrated circuits, ic06 1997 nov 25 integrated circuits 74hc/hct4046a phase-locked-loop with vco for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
1997 nov 25 2 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a features low power consumption centre frequency of up to 17 mhz (typ.) at v cc = 4.5 v choice of three phase comparators: exclusive-or; edge-triggered jk flip-flop; edge-triggered rs flip-flop excellent vco frequency linearity vco-inhibit control for on/off keying and for low standby power consumption minimal frequency drift operating power supply voltage range: vco section 3.0 to 6.0 v digital section 2.0 to 6.0 v zero voltage offset due to op-amp buffering output capability: standard i cc category: msi. general description the 74hc/hct4046a are high-speed si-gate cmos devices and are pin compatible with the 4046 of the 4000b series. they are specified in compliance with jedec standard no. 7a. the 74hc/hct4046a are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (vco) and three different phase comparators (pc1, pc2 and pc3) with a common signal input amplifier and a common comparator input. the signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. a self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. with a passive low-pass filter, the 4046a forms a second-order loop pll. the excellent vco linearity is achieved by the use of linear op-amp techniques. the vco requires one external capacitor c1 (between c1 a and c1 b ) and one external resistor r1 (between r 1 and gnd) or two external resistors r1 and r2 (between r 1 and gnd, and r 2 and gnd). resistor r1 and capacitor c1 determine the frequency range of the vco. resistor r2 enables the vco to have a frequency offset if required. the high input impedance of the vco simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. in order not to load the low-pass filter, a demodulator output of the vco input voltage is provided at pin 10 (dem out ). in contrast to conventional techniques where the dem out voltage is one threshold voltage lower than the vco input voltage, here the dem out voltage equals that of the vco input. if dem out is used, a load resistor (r s ) should be connected from dem out to gnd; if unused, dem out should be left open. the vco output (vco out ) can be connected directly to the comparator input (comp in ), or connected via a frequency-divider. the vco output signal has a duty factor of 50% (maximum expected deviation 1%), if the vco input is held at a constant dc level. a low level at the inhibit input (inh) enables the vco and demodulator, while a high level turns both off to minimize standby power consumption. the only difference between the hc and hct versions is the input level specification of the inh input. this input disables the vco section. the sections of the comparator are identical, so that there is no difference in the sig in (pin 14) or comp in (pin 3) inputs between the hc and hct versions. phase comparators the signal input (sig in ) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard hc family input logic levels. capacitive coupling is required for signals with smaller swings. phase comparator 1 (pc1) this is an exclusive-or network. the signal and comparator input frequencies (f i ) must have a 50% duty factor to obtain the maximum locking range. the transfer characteristic of pc1, assuming ripple (f r =2f i ) is suppressed, is: where v demout is the demodulator output at pin 10; v demout =v pc1out (via low-pass filter). the phase comparator gain is: the average output voltage from pc1, fed to the vco input via the low-pass filter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of signals (sig in ) and the comparator input (comp in ) as shown in fig.6. the average of v demout is equal to 1 2 v cc when there is no signal or noise at sig in and with this input the vco oscillates at the centre frequency (f o ). typical waveforms for the pc1 loop locked at f o are shown in fig.7. v demout v cc p ---------- - f sigin f compin C () = k p v cc p ---------- - vr () B . =
1997 nov 25 3 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a the frequency capture range (2f c ) is defined as the frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. this configuration retains lock even with very noisy input signals. typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the vco centre frequency. phase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detector. when the pll is using this comparator, the loop is controlled by positive signal transitions and the duty factors of sig in and comp in are not important. pc2 comprises two d-type flip-flops, control-gating and a 3-state output stage. the circuit functions as an up-down counter (fig.5) where sig in causes an up-count and comp in a down-count. the transfer function of pc2, assuming ripple (f r =f i ) is suppressed, is: where v demout is the demodulator output at pin 10; v demout =v pc2out (via low-pass filter). the phase comparator gain is: v demout is the resultant of the initial phase differences of sig in and comp in as shown in fig.8. typical waveforms for the pc2 loop locked at f o are shown in fig.9. when the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the p-type output driver at pc2 out is held on for a time corresponding to the phase difference ( f demout ). when the phase of sig in lags that of comp in , the n-type driver is held on. when the frequency of sig in is higher than that of comp in , the p-type output driver is held on for most of the input signal cycle time, and for the remainder of the cycle both n and p- type drivers are off (3-state). if the sig in frequency is lower than the comp in frequency, then it is the n-type driver that is held on for most of the cycle. subsequently, the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal v demout v cc 4 p ---------- - f sigin f compin C () = k p v cc 4 p ---------- - vr () . = and comparator inputs are equal in both phase and frequency. at this stable point the voltage on c2 remains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. also in this condition, the signal at the phase comparator pulse output (pcp out ) is a high level and so can be used for indicating a locked condition. thus, for pc2, no phase difference exists between sig in and comp in over the full frequency range of the vco. moreover, the power dissipation due to the low-pass filter is reduced because both p and n-type drivers are off for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. with no signal present at sig in the vco adjusts, via pc2, to its lowest frequency. phase comparator 3 (pc3) this is a positive edge-triggered sequential phase detector using an rs-type flip-flop. when the pll is using this comparator, the loop is controlled by positive signal transitions and the duty factors of sig in and comp in are not important. the transfer characteristic of pc3, assuming ripple (f r =f i ) is suppressed, is: where v demout is the demodulator output at pin 10; v demout =v pc3out (via low-pass filter). the phase comparator gain is: the average output from pc3, fed to the vco via the low-pass filter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of sig in and comp in as shown in fig.10. typical waveforms for the pc3 loop locked at f o are shown in fig.11. the phase-to-output response characteristic of pc3 (fig.10) differs from that of pc2 in that the phase angle between sig in and comp in varies between 0 and 360 and is 180 at the centre frequency. also pc3 gives a greater voltage swing than pc2 for input phase differences but as a consequence the ripple content of the vco input signal is higher. the pll lock range for this type of phase comparator and the capture range are dependent on the low-pass filter. with no signal present at sig in the vco adjusts, via pc3, to its lowest frequency. v demout v cc 2 p ---------- - f sigin f compin C () = k p v cc 2 p ---------- - vr () . =
1997 nov 25 4 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a quick reference data gnd = 0 v; t amb =25 c notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz. f o = output frequency in mhz. c l = output load capacitance in pf. v cc = supply voltage in v. ? (c l v cc 2 f o ) = sum of outputs. 2. applies to the phase comparator section only (vco disabled). for power dissipation of the vco and demodulator sections see figs 22, 23 and 24. ordering information see 74hc/hct/hcu/hcmos logic package information . applications fm modulation and demodulation frequency synthesis and multiplication frequency discrimination tone decoding data synchronization and conditioning voltage-to-frequency conversion motor-speed control. package outlines see 74hc/hct/hcu/hcmos logic package outlines . symbol parameter conditions typical unit hc hct f o vco centre frequency c1 = 40 pf; r1 = 3 k w ;v cc = 5 v 19 19 mhz c i input capacitance (pin 5) 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 24 24 pf
1997 nov 25 5 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a pin description pin no. symbol name and function 1 pcp out phase comparator pulse output 2 pc1 out phase comparator 1 output 3 comp in comparator input 4 vco out vco output 5 inh inhibit input 6c1 a capacitor c1 connection a 7c1 b capacitor c1 connection b 8 gnd ground (0 v) 9 vco in vco input 10 dem out demodulator output 11 r 1 resistor r1 connection 12 r 2 resistor r2 connection 13 pc2 out phase comparator 2 output 14 sig in signal input 15 pc3 out phase comparator 3 output 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
1997 nov 25 6 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a mga847 phase comparator 2 lock detector pc2 out ld 13 1 identical to 4046a c ld c cld 15 7046a phase comparator 2 pc2 out 13 phase comparator 3 pc3 out 15 phase comparator 1 pc1 out 2 pcp out 1 sig in comp in v co out c1 a c1 b dem out inh vco in r 2 r 1 r2 12 11 314 4 7 6 5109 (a) (b) c1 4046a vco r s r1 r4 r3 c2 fig.4 functional diagram. (a) (b) fig.5 logic diagram.
1997 nov 25 7 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.6 phase comparator 1: average output voltage versus input phase difference. v demout =v pc2out = f demout =( f sigin -f compin ). v cc p ---------- - f sigin f compin C () fig.7 typical waveforms for pll using phase comparator 1, loop locked at f o . fig.8 phase comparator 2: average output voltage versus input phase difference. v demout =v pc2out = f demout =( f sigin -f c ompin ). v cc 4 p ---------- - f sigin f compin C ()
1997 nov 25 8 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.9 typical waveforms for pll using phase comparator 2, loop locked at f o . fig.10 phase comparator 3: average output voltage versus input phase difference: v demout =v pc3out = f demout =( f sigin -f compin ). v cc 2 p ---------- - f sigin f compin C () fig.11 typical waveforms for pll using phase comparator 3, loop locked at f o .
1997 nov 25 9 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a recommended operating conditions for 74hc/hct ratings limiting values in accordance with the absolute maximum system (iec 134) voltages are referenced to gnd (ground = 0 v) symbol parameter 74hc 74hct unit conditions min. typ. max. min. typ. max. v cc dc supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 v v cc dc supply voltage if vco section is not used 2.0 5.0 6.0 4.5 5.0 5.5 v v i dc input voltage range 0 v cc 0v cc v v o dc output voltage range 0 v cc 0v cc v t amb operating ambient temperature range - 40 +85 - 40 +85 c see dc and ac characteristics t amb operating ambient temperature range - 40 +125 - 40 + 125 c t r ,t f input rise and fall times (pin 5) 6.0 1000 6.0 500 ns v cc = 2.0 v 6.0 500 6.0 500 ns v cc = 4.5 v 6.0 400 6.0 500 ns v cc = 6.0 v symbol parameter min. max. unit conditions v cc dc supply voltage - 0.5 +7 v i ik dc input diode current 20 ma for v i <- 0.5 v or v i > v cc + 0.5 v i ok dc output diode current 20 ma for v o <- 0.5 v or v o > v cc + 0.5 v i o dc output source or sink current 25 ma for - 0.5 v < v o < v cc + 0.5 v i cc ; i gnd dc v cc or gnd current 50 ma t stg storage temperature range - 65 +150 c p tot power dissipation per package plastic dil 750 mw for temperature range: - 40 to +125 c 74hc/hct above + 70 c: derate linearly with 12 mw/k plastic mini-pack (so) 500 mw above + 70 c: derate linearly with 8 mw/k
1997 nov 25 10 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a dc characteristics for 74hc quiescent supply current voltages are referenced to gnd (ground = 0 v) phase comparator section voltages are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. i cc quiescent supply current (vco disabled) 8.0 80.0 160.0 m a 6.0 pins 3, 5, and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih dc coupled high level input voltage sig in , comp in 1.5 1.2 1.5 1.5 v 2.0 3.15 2.4 3.15 3.15 4.5 4.2 3.2 4.2 4.2 6.0 v il dc coupled low level input voltage sig in , comp in 0.8 0.5 0.5 0.5 v 2.0 2.1 1.35 1.35 1.35 4.5 2.8 1.8 1.8 1.8 6.0 v oh high level output voltage pcp out ,pc nout 1.9 2.0 1.9 1.9 v 2.0 v ih or v il - i o =20 m a 4.4 4.5 4.4 4.4 4.5 - i o =20 m a 5.9 6.0 5.9 5.9 6.0 - i o =20 m a v oh high level output voltage pcp out ,pc nout 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma 5.48 5.81 5.34 5.2 6.0 - i o = 5.2 ma v ol low level output voltage pcp out ,pc nout 0 0.1 0.1 0.1 v 2.0 v ih or v il i o =20 m a 0 0.1 0.1 0.1 4.5 i o =20 m a 0 0.1 0.1 0.1 6.0 i o =20 m a v ol low level output voltage pcp out ,pc nout 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma 0.16 0.26 0.33 0.4 6.0 i o = 5.2 ma i i input leakage current sig in , comp in 3.0 4.0 5.0 m a 2.0 v cc or gnd 7.0 9.0 11.0 3.0 18.0 23.0 27.0 4.5 30.0 38.0 45.0 6.0 i oz 3-state off-state current pc2 out 0.5 5.0 10.0 m a 6.0 v ih or v il v o =v cc or gnd
1997 nov 25 11 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a vco section voltages are referenced to gnd (ground = 0 v) r i input resistance sig in , comp in 800 k w 3.0 v i at self-bias operating point; d v i = 0.5 v; see figs 12, 13 and 14 250 k w 4.5 150 k w 6.0 sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high level input voltage inh 2.1 1.7 2.1 2.1 v 3.0 3.15 2.4 3.15 3.15 4.5 4.2 3.2 4.2 4.2 6.0 v il low level input voltage inh 1.3 0.9 0.9 0.9 v 3.0 2.1 1.35 1.35 1.35 4.5 2.8 1.8 1.8 1.8 6.0 v oh high level output voltage vco out 2.9 3.0 2.9 2.9 v 3.0 v ih or v il - i o =20 m a 4.4 4.5 4.4 4.4 4.5 - i o =20 m a 5.9 6.0 5.9 5.9 6.0 - i o =20 m a v oh high level output voltage vco out 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma 5.48 5.81 5.34 5.2 6.0 - i o = 5.2 ma v ol low level output voltage vco out 0 0.1 0.1 0.1 v 3.0 v ih or v il i o =20 m a 0 0.1 0.1 0.1 4.5 i o =20 m a 0 0.1 0.1 0.1 6.0 i o =20 m a v ol low level output voltage vco out 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma 0.16 0.26 0.33 0.4 6.0 i o = 5.2 ma v ol low level output voltage c1 a ,c1 b 0.40 0.47 0.54 v 4.5 v ih or v il i o = 4.0 ma 0.40 0.47 0.54 6.0 i o = 5.2 ma i i input leakage current inh, vco in 0.1 1.0 1.0 m a 6.0 v cc or gnd r1 resistor range 3.0 300 k w 3.0 note 1 3.0 300 4.5 3.0 300 6.0 sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max.
1997 nov 25 12 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a note 1. the parallel value of r1 and r2 should be more than 2.7 k w . optimum performance is achieved when r1 and/ or r2 are/is > 10 k w . demodulator section voltages are referenced to gnd (ground = 0 v) r 2 resistor range 3.0 300 k w 3.0 note 1 3.0 300 4.5 3.0 300 6.0 c1 capacitor range 40 no limit pf 3.0 40 4.5 40 6.0 v vcoin operating voltage range at vco in 1.1 1.9 v 3.0 over the range speci?ed for r1; for linearity see figs 20 and 21 1.1 3.4 4.5 1.1 4.9 6.0 symbol parameter t amb ( c) unit test conditions 74hc v cc v other +25 - 40 to+85 - 40 to +125 min. typ. max. min. max. min. max. r s resistor range 50 300 k w 3.0 at r s > 300 k w the leakage current can in?uence v demout 50 300 4.5 50 300 6.0 v off offset voltage vco in to v demout 30 mv 3.0 v i =v vcoin = 1/2 v cc ; values taken over r s range; see fig.15 20 4.5 10 6.0 r d dynamic output resistance at dem out 25 w 3.0 v demout = 1/2 v cc 25 4.5 25 6.0 sym- bol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max.
1997 nov 25 13 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a ac characteristics for 74hc phase comparator section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sig in , comp in to pc1 out 63 200 250 300 ns 2.0 fig.16 23 40 50 60 4.5 18 34 43 51 6.0 t phl / t plh propagation delay sig in , comp in to pcp out 96 340 425 510 ns 2.0 fig.16 35 68 85 102 4.5 28 58 72 87 6.0 t phl / t plh propagation delay sig in , comp in to pc3 out 77 270 340 405 ns 2.0 fig.16 28 54 68 81 4.5 22 46 58 69 6.0 t pzh / t pzl 3-state output enable time sig in , comp in to pc2 out 83 280 350 420 ns 2.0 fig.17 30 56 70 84 4.5 24 48 60 71 6.0 t phz / t plz 3-state output disable time sig in , comp in to pc2 out 99 325 405 490 ns 2.0 fig.17 36 65 81 98 4.5 29 55 69 83 6.0 t thl / t tlh output transition time 19 75 95 110 ns 2.0 fig.16 7 15 19 22 4.5 6 13 16 19 6.0 v i(p-p) ac coupled input sensitivity (peak-to-peak value) at sig in or comp in 9 mv 2.0 f i = 1 mhz 11 3.0 15 4.5 33 6.0
1997 nov 25 14 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a vco section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf dc characteristics for 74hct quiescent supply current voltages are referenced to gnd (ground = 0 v) note 1. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given above. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. typ. max. min. max. d f/t frequency stability with temperature change 0.20 %/k 3.0 v i =v vcoin = 1/2 v cc ; r1 = 100 k w ;r2= ; c1 = 100 pf; see fig.18 0.15 4.5 0.14 6.0 f o vco centre frequency (duty factor = 50%) 7.0 10.0 mhz 3.0 v vcoin = 1/2 v cc ; r1 = 3 k w ;r2= ; c1 = 40 pf; see fig.19 11.0 17.0 4.5 13.0 21.0 6.0 d f vco vco frequency linearity 1.0 % 3.0 r1 = 100 k w ;r2= ; c1 = 100 pf; see figs 20 and 21 0.4 4.5 0.3 6.0 d vco duty factor at vco out 50 % 3.0 50 4.5 50 6.0 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. i cc quiescent supply current (vco disabled) 8.0 80.0 160.0 m a 6.0 pins 3, 5 and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded d i cc additional quiescent supply current per input pin for unit load coef?cient is 1 (note 1) v i =v cc - 2.1 v 100 360 450 490 m a 4.5 to 5.5 pins 3 and 14 at v cc ; pin 9 at gnd; i i at pins 3 and 14 to be excluded input unit load coefficient inh 1.00
1997 nov 25 15 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a dc characteristics for 74hct phase comparator section voltages are referenced to gnd (groun d=0v) symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v i other +25 - 40 to +85 - 40 to +125 min typ. max min max min. max. v ih dc coupled high level input voltage sig in , comp in 3.15 2.4 v 4.5 v il dc coupled low level input voltage sig in , comp in 2.1 1.35 v 4.5 v oh high level output voltage pcp out , pc nout 4.4 4.5 4.4 4.4 v 4.5 v ih or v il - i o =20 m a v oh high level output voltage pcp out , pc nout 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma v ol low level output voltage pcp out ,pc nout 0 0.1 0.1 0.1 v 4.5 v ih or v il i o =20 m a v ol low level output voltage pcp out ,pc nout 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma i i input leakage current sig in , comp in 30 38 45 m a 5.5 v cc or gn d i oz 3-state off-state current pc2 out 0.5 5.0 10.0 m a 5.5 v ih or v il v o =v cc or gnd r i input resistance sig in , comp in 250 k w 4.5 v i at self-bias operating point; d v i = 0.5 v; see figs 12 , 13 and 14
1997 nov 25 16 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a dc characteristics for 74hct vco section voltages are referenced to gnd (ground = 0 v) note 1. the parallel value of r1 and r2 should be more than 2.7 k w . optimum performance is achieved when r1 and/or r2 are/is > 10 k w . symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v i other +25 - 40 to +85 - 40 to +125 min typ. max min max min. max. v ih high level input voltage inh 2.0 1.6 2.0 2.0 v 4.5 to 5.5 v il low level input voltage inh 1.2 0.8 0.8 0.8 v 4.5 to 5.5 v oh high level output voltage vco out 4.4 4.5 4.4 4.4 v 4.5 v ih or v il - i o =20 m a v oh high level output voltage vco out 3.98 4.32 3.84 3.7 v 4.5 v ih or v il - i o = 4.0 ma v ol low level output voltage vco out 0 0.1 0.1 0.1 v 4.5 v ih or v il i o =20 m a v ol low level output voltage vco out 0.15 0.26 0.33 0.4 v 4.5 v ih or v il i o = 4.0 ma v ol low level output voltage c1 a ,c1 b (test purposes only) 0.40 0.47 0.54 v 4.5 v ih or v il i o = 4.0 ma i i input leakage current inh, vco in 0.1 1.0 1.0 m a 5.5 v cc or gnd r1 resistor range 3.0 300 k w 4.5 note 1 r 2 resistor range 3.0 300 k w 4.5 note 1 c1 capacitor range 40 no limit pf 4.5 v vcoin operating voltage range at vco in 1.1 3.4 v 4.5 over the range speci?ed for r1; for linearity see figs 20 and 21
1997 nov 25 17 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a dc characteristics for 74hct demodulator section voltages are referenced to gnd (ground = 0 v) ac characteristics for 74hct phase comparator section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. r s resistor range 50 300 k w 4.5 at r s > 300 k w the leakage current can in?uence v demout v off offset voltage vco in to v demout 20 mv 4.5 v i =v vcoin = 1/2 v cc ; values taken over r s range; see fig.15 r d dynamic output resistance at dem out 25 w 4.5 v demout = 1/2 v cc symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sig in , comp in to pc1 out 23 40 50 60 ns 4.5 fig.16 t phl / t plh propagation delay sig in , comp in to pcp out 35 68 85 102 ns 4.5 fig.16 t phl / t plh propagation delay sig in , comp in to pc3 out 28 54 68 81 ns 4.5 fig.16 t pzh / t pzl 3-state output enable time sig in , comp in to pc2 out 30 56 70 84 ns 4.5 fig.17
1997 nov 25 18 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a vco section gnd = 0 v; t r =t f = 6 ns; c l = 50 pf t phz / t plz 3-state output disable time sig in , comp in to pc2 out 36 65 81 98 ns 4.5 fig.17 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.16 v i (p-p) ac coupled input sensitivity (peak-to-peak value) at sig in or comp in 15 mv 4.5 f i = 1 mhz symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max min. max min. max. d f/t frequency stability with temperature change 0.15 %/k 4.5 v i =v vcoin withi n recommended range; r1 = 100 k w ; r2 = ; c1 = 100 pf; see fig.18b f o vco centre frequency (duty factor = 50%) 11.0 17.0 mhz 4.5 v vcoin = 1/2 v cc ; r1 = 3 k w ; r2 = ; c1 = 40 pf; see fig.19 d f vco vco frequency linearity 0.4 % 4.5 r1 = 100 k w ; r2 = ; c1 = 100 pf; see figs 20 and 21 d vco duty factor at vco out 50 % 4.5 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max.
1997 nov 25 19 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a figure references for dc characteristics fig.12 typical input resistance curve at sig in , comp in . fig.13 input resistance at sig in , comp in with d v i = 0.5 v at self-bias point. fig.14 input current at sig in , comp in with d v i = 0.5 v at self-bias point. fig.15 offset voltage at demodulator output as a function of vco in and r s . ?? r s =50k w ----r s = 300 k w
1997 nov 25 20 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a ac waveforms fig.16 waveforms showing input (sig in , comp in ) to output (pcp out , pc1 out , pc3 out ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc fig.17 waveforms showing the 3-state enable and disable times for pc2 out . (1) hc : v m = 50%; v i = gnd to v cc
1997 nov 25 21 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.18 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. ?? without offset (r2 = ): (a) r1 = 3 k w ; (b) r1 = 10 k w ; (c) r1 = 300 k w . --- with offset (r1 = ): (a) r2 = 3 k w ; (b) r2 = 10 k w ; (c) r2 = 300 k w . in (b), the frequency stability for r1 = r2 = 10 k w at 5 v is also given (curve a). this curve is set by the total vco bias current, and is not simply the addition of the two 10 k w stability curves. c1 = 100 pf; v vco in = 0.5 v cc . to obtain optimum temperature stability, c1 must be as small as possible but larger than 100 pf. b ook, halfpage msb710 t amb ( o c) 0 150 100 50 0 - 50 - 25 - 20 - 15 - 10 - 5 5 10 15 20 25 d f (%) 5 v 6 v 3 v 4.5 v 5 v 6 v v = cc 3 v (a) handbook, halfpage msb711 t ( c) amb 0 f (%) o 150 100 50 0 50 25 20 15 10 5 5 10 15 20 25 d 5 v 6 v 3 v 5 v 6 v v = cc 3 v (b) a handbook, halfpage msb712 t ( c) amb 0 f (%) o 150 100 50 0 50 25 20 15 10 5 5 10 15 20 25 d 5 v 6 v (c) v = cc 3 v 3 v 6 v 5 v
1997 nov 25 22 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.18 continued. (d) r 2 =3k w r 1 = (e) r 2 =10k w r 1 = (f) r 2 = 300 k w r 1 = to obtain optimum temperature stability, c1 must be as small as possible but larger than 100 pf.
1997 nov 25 23 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.19 graphs showing vco frequency (f vco ) as a function of the vco input voltage (v vcoin ). (a) r 1 =3k w ; c 1 = 40 pf (c) r 1 = 300 k w ; c 1 =40pf (d) r 1 = 300 k w ; c 1 = 100 nf (b) r 1 =3k w ; c 1 = 100 nf to obtain optimum temperature stability, c1 must be as small as possible but larger than 100 pf.
1997 nov 25 24 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.20 definition of vco frequency linearity: d v = 0.5 v over the v cc range: for vco linearity f 0 f 1 f 2 + 2 -------------- - = linearity f 0 f 0 C f 0 ---------------- 100% = fig.21 frequency linearity as a function of r1, c1 and v cc : r2 = and d v = 0.5 v. fig.22 power dissipation versus the value of r1: c l = 50 pf; r2 = ; v vcoin = 1/2 v cc ; t amb =25 c. ?? c1 = 40 pf - - - -c1 = 1 m f fig.23 power dissipation versus the value of r2: c l = 50 pf; r1 = ; v vcoin =gnd=0v; t amb =25 c. ?? c1 = 40 pf - - - - c1 = 1 m f fig.24 typical dc power dissipation of demodulator sections as a function of r s : r1=r2= ; t amb =25 c; v vcoin = 1/2 v cc .
1997 nov 25 25 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a application information this information is a guide for the approximation of values of external components to be used with the 74hc/hct4046a in a phase-lock-loop system. references should be made to figs 29, 30 and 31 as indicated in the table. values of the selected components should be within the following ranges: r1 between 3 k w and 300 k w ; r2 between 3 k w and 300 k w ; r1 + r2 parallel value > 2.7 k w ; c1 greater than 40 pf. subject phase comparator design considerations vco frequency characteristic vco frequency without extra offset pc1, pc2 or pc3 with r2 = and r1 within the range 3 k w< r1 < 300 k w , the characteristics of the vco operation will be as shown in fig.25. (due to r1, c1 time constant a small offset remains when r2 = .). fig.25 frequency characteristic of vco operating without offset: f 0 = centre frequency; 2f l = frequency lock range. selection of r1 and c1 pc1 given f o , determine the values of r1 and c1 using fig.29. pc2 or pc3 given f max and f o , determine the values of r1 and c1 using fig.29, use fig.31 to obtain 2f l and then use this to calculate f min .
1997 nov 25 26 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a vco frequency characteristic vco frequency with extra offset pc1, pc2 or pc3 with r1 and r2 within the ranges 3 k w< r1 < 300 k w , 3k w< r2 < 300 k w , the characteristics of the vco operation will be as shown in fig.26. fig.26 frequency characteristic of vco operating with offset: f o = centre frequency; 2f l = frequency lock range. selection of r1, r2 and c1 pc1, pc2 or pc3 given f o and f l , determine the value of product r1c1 by using fig.31. calculate f off from the equation f off =f o ? 1.6f l . obtain the values of c1 and r2 by using fig.30. calculate the value of r1 from the value of c1 and the product r1c1. pll conditions with no signal at the sig in input pc1 vco adjusts to f o with f demout =90 and v vcoin = 1/2 v cc (see fig.6). pc2 vco adjusts to f o with f demout = - 360 and v vcoin = min. (see fig.8). pc3 vco adjusts to f o with f demout = - 360 and v vcoin = min. (see fig.10). subject phase comparator design considerations
1997 nov 25 27 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a pll frequency capture range pc1, pc2 or pc3 loop ?lter component selection (a) t = r3 x c2 (b) amplitude characteristic (c) pole-zero diagram a small capture range (2f c ) is obtained if fig. 27 simple loop ?lter for pll without offset; r3 3 500 w . (a) t 1 = r3 x c2; (b) amplitude characteristic (c) pole-zero diagram t 2 = r4 x c2; t 3 = (r3 + r4) x c2 fig.28 simple loop ?lter for pll with offset; r3 + r4 3 500 w . pll locks on harmonics at centre frequency pc1 or pc3 yes pc2 no noise rejection at signal input pc1 high pc2 or pc3 low ac ripple content when pll is locked pc1 f r =2f i , large ripple content at f demout =90 pc2 f r =f i , small ripple content at f demout =0 pc3 f r =f i , large ripple content at f demout = 180 subject phase comparator design considerations 2f c 1 p -- - 2 p f l t ?
1997 nov 25 28 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.29 typical value of vco centre frequency (f o ) as a function of c1: r2 = ; v vcoin = 1/2 v cc ; inh = gnd; t amb =25 c. to obtain optimum vco performance, c1 must be as small as possible but larger than 100 pf. interpolation for various values of r1 can be easily calculated because a constant r1c1 product will produce almost the same vc o output frequency.
1997 nov 25 29 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.30 typical value of frequency offset as a function of c1: r1 = ;v vcoin = 1/2 v cc ; inh = gnd; t amb =25 c. to obtain optimum vco performance, c1 must be as small as possible but larger than 100 pf. interpolation for various values of r2 can be easily calculated because a constant r2c1 product will produce almost the same vc o output frequency.
1997 nov 25 30 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.31 typical frequency lock range (2f l ) versus the product r1c1: v vcoin range = 0.9 to (v cc - 0.9) v; r2 = ; vco gain: k v 2f l v vcoin range ------------------------------------ - 2 p rsv () B . =
1997 nov 25 31 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a pll design example the frequency synthesizer, used in the design example shown in fig.32, has the following parameters: output frequency: 2 mhz to 3 mhz frequency steps : 100 khz settling time : 1 ms overshoot : < 20% the open-loop gain is h (s) x g (s) = k p k f k o k n . where: k p = phase comparator gain k f = low-pass filter transfer gain k o =k v /s vco gain k n = 1/n divider ratio the programmable counter ratio k n can be found as follows: the vco is set by the values of r1, r2 and c1, r2 = 10 k w (adjustable). the values can be determined using the information in the section design considerations. with f o = 2.5 mhz and f l = 500 khz this gives the following values (v cc = 5.0 v): r1 = 10 k w r2 = 10 k w c1 = 500 pf n min. f out f step ---------- - 2mhz 100 khz --------------------- - 20 == = n max. f out f step ---------- - 3mhz 100 khz --------------------- - 30 == = the vco gain is: the gain of the phase comparator is: the transfer gain of the filter is given by: where: the characteristics equation is: 1+h(s) g (s) = 0. this results in: the natural frequency w n is defined as follows: k v 2f l 2 p 0.9 v cc 0.9 C () C ---------------------------------------------- - B = = 1mhz 3.2 ----------------- 2 p 210 6 ? r/s/v = k p v cc 4 p ------------ 0.4 v/r. == k f 1 t 2 s + 1 t 1 t 2 + () s + ------------------------------------ - . = t 1 r3c2 and t 2 r4c2. = = s 2 1k p k v k n t 2 + t 1 t 2 + () ----------------------------------------------------- s+ + k p k v k n t 1 t 2 + () -------------------------------- 0. = w n k p k v k n t 1 t 2 + () -------------------------------- . = and the damping value z is defined as follows: in fig.33 the output frequency response to a step of input frequency is shown. the overshoot and settling time percentages are now used to determine w n . from fig.33 it can be seen that the damping ratio z = 0.45 will produce an overshoot of less than 20% and settle to within 5% at w n t = 5. the required settling time is 1 ms. this results in: rewriting the equation for natural frequency results in: the maximum overshoot occurs at n max .: when c2 = 470 nf, then now r3 can be calculated: z 1 2 w n ---------- 1k p k v k n t 2 + t 1 t 2 + () ----------------------------------------------------- = w n 5 t -- - 5 0.001 -------------- - 510 3 r/s. == = t 1 t 2 + () k p k v k n w n 2 -------------------------------- . = t 1 t 2 + () 0.4210 6 5000 2 30 --------------------------------- 0.0011 s. == r4 t 1 t 2 + () 2 w n z 1 C k p k v k n c2 ---------------------------------------------------------------- - 315 w == r3 t 1 c2 ------- - r4 = 2 k w . C =
1997 nov 25 32 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a fig.32 frequency synthesizer. note for an extensive description and application example please refer to application note ordering number 9398 649 90011. also available a computer design program for plls ordering number 9398 961 10061. fig.33 type 2, second order frequency step response. full pagewidth 012 4 1.6 1.0 0.6 0 0.8 msb740 3 1.4 1.2 0.4 0.2 5678 w n t 0.6 0 0.4 1.0 0.2 0.4 0.2 0.6 0.8 = 5.0 z 0.5 0.707 1.0 = 0.3 z = 2.0 z dq e / w n dq e (t) dw e / w n dw e (t) since the output frequency is proportional to the vco control voltage, the pll frequency response can be observed with an oscilloscope by monitoring pin 9 of the vco. the average frequency response, as calculated by the laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple rc filter, whose time constant is long compared to the phase detector sampling rate but short compared to the pll response time. fig.34 frequency compared to the time response.
1997 nov 25 33 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so, ssop and tssop r eflow soldering reflow soldering techniques are suitable for all so, ssop and tssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering can be used for all so packages. wave soldering is not recommended for ssop and tssop packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering is used - and cannot be avoided for ssop and tssop packages - the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions: only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1). do not consider wave soldering tssop packages with 48 leads or more, that is tssop48 (sot362-1) and tssop56 (sot364-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 nov 25 34 philips semiconductors product speci?cation phase-locked-loop with vco 74hc/hct4046a definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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